In processor based systems or platforms having current and proposed initialization processes such as those provided by the Extended Firmware Interface (EFI), further specified at a web site accessible at www.uefi.org, early memory usage is necessary. That is, early platform initialization code may require access to a memory before the primary memory subsystems of the platform have been initialized. In one approach, such initialization code may rely upon the ability to access processor cache or a processor cache segment associated with a core of a multiple core system as random access memory (RAM), and to use this for a stack and/or a heap as may be required by the initialization code. This technique is referred to as cache-as-RAM (CAR).
In emergent cache topologies for multi-core systems, a large cache with many cache segments may be shared among the cores. Various methods of sharing are known the art that may allow for amicable cache line sharing among a plurality of cores. However, a system that is initialized in a state where a cache to be used for CAR system initialization comes up in a shareable state may create problems for early boot flows. For example, in one Pre-EFI Initialization (PEI) flow, processor cache-as-RAM is used to initialize the main memory technology (which may be one of many well known types such as double-data-rate dynamic random access (DDR) memory, among others) or an interconnection system such as the Common System Interconnect (CSI) control, decoding, and routing hardware.
Currently, a proposed boot model in such multi-core or many-core systems is to enable only one core and select this one core with a hardware state machine that runs at power up or a startup event to select the core. However, in such a scheme, this one core may become a single point of failure that compromises the overall reliability of the system.
Also, as instant-restart becomes an important feature in servers, taking advantage of multiple cores for a faster boot process is attractive. It would be desirable therefore, for pre-EFI and similar initialization software to both maximally parallelize the initialization across multiple cores and be robust in the face of a failed core or errant core or a failed or malfunctioning segment of the cache associated with a core.